1. Field of the Invention
The present invention relates generally to computer systems, and more specifically to a memory controller for a computer system using a page mode access to DRAMs (dynamic random access memories) in which the memory access time (the precharge time of the row address plus the time to specify a row address) is reduced by repeatedly activating the column address strobe (CAS) line to successively specify column addresses while keeping the row address strobe line (RAS) active.
2. Description of the Related Art
According to conventional page mode access techniques used for accessing dynamic random access memories which are divided into a plurality of groups or banks, the banks are provided respectively with row address strobe (RAS) lines. However, the RAS line of each memory bank is independently activated to provide a page mode access exclusively to the memories of the associated bank when page hit occurs between successive accesses to the memories. However, because of the low degree of relationship between program addresses and data addresses, page hits occur less frequently if row accesses change from one bank to another.